Contributors: 8
Author Tokens Token Proportion Commits Commit Proportion
Scott Wood 549 89.71% 1 9.09%
Rashmica Gupta 24 3.92% 1 9.09%
Chris Freehill 12 1.96% 1 9.09%
Madhavan Srinivasan 9 1.47% 1 9.09%
Peter Zijlstra 8 1.31% 2 18.18%
Linus Torvalds (pre-git) 5 0.82% 3 27.27%
Linus Torvalds 3 0.49% 1 9.09%
Thomas Gleixner 2 0.33% 1 9.09%
Total 612 11 


// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Performance counter support for e500 family processors.
 *
 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
 * Copyright 2010 Freescale Semiconductor, Inc.
 */
#include <linux/string.h>
#include <linux/perf_event.h>
#include <asm/reg.h>
#include <asm/cputable.h>

/*
 * Map of generic hardware event types to hardware events
 * Zero if unsupported
 */
static int e500_generic_events[] = {
	[PERF_COUNT_HW_CPU_CYCLES] = 1,
	[PERF_COUNT_HW_INSTRUCTIONS] = 2,
	[PERF_COUNT_HW_CACHE_MISSES] = 41, /* Data L1 cache reloads */
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
	[PERF_COUNT_HW_BRANCH_MISSES] = 15,
	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 18,
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 19,
};

#define C(x)	PERF_COUNT_HW_CACHE_##x

/*
 * Table of generalized cache-related events.
 * 0 means not supported, -1 means nonsensical, other values
 * are event codes.
 */
static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	/*
	 * D-cache misses are not split into read/write/prefetch;
	 * use raw event 41.
	 */
	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	27,		0	},
		[C(OP_WRITE)] = {	28,		0	},
		[C(OP_PREFETCH)] = {	29,		0	},
	},
	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	2,		60	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	0,		0	},
	},
	/*
	 * Assuming LL means L2, it's not a good match for this model.
	 * It allocates only on L1 castout or explicit prefetch, and
	 * does not have separate read/write events (but it does have
	 * separate instruction/data events).
	 */
	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0	},
		[C(OP_WRITE)] = {	0,		0	},
		[C(OP_PREFETCH)] = {	0,		0	},
	},
	/*
	 * There are data/instruction MMU misses, but that's a miss on
	 * the chip's internal level-one TLB which is probably not
	 * what the user wants.  Instead, unified level-two TLB misses
	 * are reported here.
	 */
	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	26,		66	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(BPU)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	12,		15 	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(NODE)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	-1,		-1 	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
};

static int num_events = 128;

/* Upper half of event id is PMLCb, for threshold events */
static u64 e500_xlate_event(u64 event_id)
{
	u32 event_low = (u32)event_id;
	u64 ret;

	if (event_low >= num_events)
		return 0;

	ret = FSL_EMB_EVENT_VALID;

	if (event_low >= 76 && event_low <= 81) {
		ret |= FSL_EMB_EVENT_RESTRICTED;
		ret |= event_id &
		       (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH);
	} else if (event_id &
	           (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH)) {
		/* Threshold requested on non-threshold event */
		return 0;
	}

	return ret;
}

static struct fsl_emb_pmu e500_pmu = {
	.name			= "e500 family",
	.n_counter		= 4,
	.n_restricted		= 2,
	.xlate_event		= e500_xlate_event,
	.n_generic		= ARRAY_SIZE(e500_generic_events),
	.generic_events		= e500_generic_events,
	.cache_events		= &e500_cache_events,
};

static int init_e500_pmu(void)
{
	unsigned int pvr = mfspr(SPRN_PVR);

	/* ec500mc */
	if (PVR_VER(pvr) == PVR_VER_E500MC || PVR_VER(pvr) == PVR_VER_E5500)
		num_events = 256;
	/* e500 */
	else if (PVR_VER(pvr) != PVR_VER_E500V1 && PVR_VER(pvr) != PVR_VER_E500V2)
		return -ENODEV;

	return register_fsl_emb_pmu(&e500_pmu);
}

early_initcall(init_e500_pmu);