Contributors: 19
Author Tokens Token Proportion Commits Commit Proportion
Linus Torvalds 67 34.36% 2 6.67%
Linus Torvalds (pre-git) 40 20.51% 7 23.33%
Dave Jones 30 15.38% 2 6.67%
Ingo Molnar 11 5.64% 1 3.33%
Andi Kleen 8 4.10% 2 6.67%
Hidetoshi Seto 8 4.10% 2 6.67%
Thomas Gleixner 7 3.59% 1 3.33%
Chen Yucong 4 2.05% 1 3.33%
Peter Zijlstra 3 1.54% 1 3.33%
Jeremy Fitzhardinge 3 1.54% 2 6.67%
Brian Gerst 3 1.54% 1 3.33%
Rusty Russell 2 1.03% 1 3.33%
Tony Luck 2 1.03% 1 3.33%
Jan Beulich 2 1.03% 1 3.33%
Borislav Petkov 1 0.51% 1 3.33%
Andrew Lutomirski 1 0.51% 1 3.33%
Alexander van Heukelum 1 0.51% 1 3.33%
Alan Cox 1 0.51% 1 3.33%
Greg Kroah-Hartman 1 0.51% 1 3.33%
Total 195 30


// SPDX-License-Identifier: GPL-2.0
/*
 * P5 specific Machine Check Exception Reporting
 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
 */
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/smp.h>
#include <linux/hardirq.h>

#include <asm/processor.h>
#include <asm/traps.h>
#include <asm/tlbflush.h>
#include <asm/mce.h>
#include <asm/msr.h>

#include "internal.h"

/* By default disabled */
int mce_p5_enabled __read_mostly;

/* Machine check handler for Pentium class Intel CPUs: */
noinstr void pentium_machine_check(struct pt_regs *regs)
{
	u32 loaddr, hi, lotype;

	instrumentation_begin();
	rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
	rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);

	pr_emerg("CPU#%d: Machine Check Exception:  0x%8X (type 0x%8X).\n",
		 smp_processor_id(), loaddr, lotype);

	if (lotype & (1<<5)) {
		pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
			 smp_processor_id());
	}

	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
	instrumentation_end();
}

/* Set up machine check reporting for processors with Intel style MCE: */
void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
{
	u32 l, h;

	/* Default P5 to off as its often misconnected: */
	if (!mce_p5_enabled)
		return;

	/* Check for MCE support: */
	if (!cpu_has(c, X86_FEATURE_MCE))
		return;

	/* Read registers before enabling: */
	rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
	rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
	pr_info("Intel old style machine check architecture supported.\n");

	/* Enable MCE: */
	cr4_set_bits(X86_CR4_MCE);
	pr_info("Intel old style machine check reporting enabled on CPU#%d.\n",
		smp_processor_id());
}