Contributors: 19
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Ander Conselvan de Oliveira |
123 |
33.70% |
15 |
26.79% |
| Jani Nikula |
63 |
17.26% |
7 |
12.50% |
| Eric Anholt |
48 |
13.15% |
1 |
1.79% |
| Daniel Vetter |
24 |
6.58% |
5 |
8.93% |
| Ville Syrjälä |
22 |
6.03% |
7 |
12.50% |
| Chon Ming Lee |
20 |
5.48% |
2 |
3.57% |
| Maarten Lankhorst |
16 |
4.38% |
2 |
3.57% |
| Manasi D Navare |
12 |
3.29% |
1 |
1.79% |
| Chris Wilson |
8 |
2.19% |
2 |
3.57% |
| Zou Nan hai |
6 |
1.64% |
1 |
1.79% |
| Imre Deak |
5 |
1.37% |
3 |
5.36% |
| Lucas De Marchi |
4 |
1.10% |
1 |
1.79% |
| Satheeshakrishna M |
3 |
0.82% |
1 |
1.79% |
| Paulo Zanoni |
3 |
0.82% |
2 |
3.57% |
| Jesse Barnes |
3 |
0.82% |
1 |
1.79% |
| Shaohua Li |
2 |
0.55% |
2 |
3.57% |
| Zhenyu Wang |
1 |
0.27% |
1 |
1.79% |
| Pradeep Bhat |
1 |
0.27% |
1 |
1.79% |
| Damien Lespiau |
1 |
0.27% |
1 |
1.79% |
| Total |
365 |
|
56 |
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2019 Intel Corporation
*/
#ifndef __INTEL_DPIO_PHY_H__
#define __INTEL_DPIO_PHY_H__
#include <linux/types.h>
enum pipe;
enum port;
struct drm_i915_private;
struct intel_crtc_state;
struct intel_digital_port;
struct intel_encoder;
enum dpio_channel {
DPIO_CH0,
DPIO_CH1,
};
enum dpio_phy {
DPIO_PHY0,
DPIO_PHY1,
DPIO_PHY2,
};
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
enum dpio_phy phy);
u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
u8 lane_lat_optim_mask);
u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port);
enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port);
enum dpio_channel vlv_pipe_to_channel(enum pipe pipe);
void chv_set_phy_signal_level(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 deemph_reg_value, u32 margin_reg_value,
bool uniq_trans_scale);
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool reset);
void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
void chv_phy_post_pll_disable(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 demph_reg_value, u32 preemph_reg_value,
u32 uniqtranscale_reg_value, u32 tx3_demph);
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void vlv_phy_reset_lanes(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
#endif /* __INTEL_DPIO_PHY_H__ */