| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Rob Clark | 1092 | 98.82% | 3 | 75.00% |
| Hai Li | 13 | 1.18% | 1 | 25.00% |
| Total | 1105 | 4 |
#ifndef DSI_PHY_28NM_XML #define DSI_PHY_28NM_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng headergen tool in this git repository: http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-03-03 01:18:13) - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-01-30 18:25:22) - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-01-30 18:25:22) - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-01-30 18:25:22) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml ( 17560 bytes, from 2021-09-16 22:37:02) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-07-22 15:21:56) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-07-22 15:21:56) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-07-22 15:21:56) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-07-22 15:21:56) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-07-22 15:21:56) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-07-22 15:21:56) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-03 01:18:13) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-01-30 18:25:22) - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-01-30 18:25:22) - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-01-30 18:25:22) - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-01-30 18:25:22) - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-01-30 18:25:22) Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; } #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; } #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) { return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; } #define REG_DSI_28nm_PHY_CTRL_0 0x00000170 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c #define REG_DSI_28nm_PHY_CTRL_4 0x00000180 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) { return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; } #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) { return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; } #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) { return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; } #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) { return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; } #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) { return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; } #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 #endif /* DSI_PHY_28NM_XML */
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