/* * Copyright 2019 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "priv.h" #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) MODULE_FIRMWARE("nvidia/gp10b/acr/bl.bin"); MODULE_FIRMWARE("nvidia/gp10b/acr/ucode_load.bin"); #endif static const struct nvkm_acr_hsf_fwif gp10b_acr_load_fwif[] = { { 0, gm200_acr_hsfw_ctor, &gm20b_acr_load_0, NVKM_ACR_HSF_PMU, 0, 0x00000010 }, {} }; static const struct nvkm_acr_func gp10b_acr = { .load = gp10b_acr_load_fwif, .wpr_parse = gm200_acr_wpr_parse, .wpr_layout = gm200_acr_wpr_layout, .wpr_alloc = gm20b_acr_wpr_alloc, .wpr_build = gm200_acr_wpr_build, .wpr_patch = gm200_acr_wpr_patch, .wpr_check = gm200_acr_wpr_check, .init = gm200_acr_init, }; static const struct nvkm_acr_fwif gp10b_acr_fwif[] = { { 0, gm20b_acr_load, &gp10b_acr }, { -1, gm200_acr_nofw, &gm200_acr }, {} }; int gp10b_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_acr **pacr) { return nvkm_acr_new_(gp10b_acr_fwif, device, type, inst, pacr); }