/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_PCIE_DEC0_CMD_REGS_H_ #define ASIC_REG_PCIE_DEC0_CMD_REGS_H_ /* ***************************************** * PCIE_DEC0_CMD * (Prototype: VSI_CMD) ***************************************** */ #define mmPCIE_DEC0_CMD_SWREG0 0x4F00000 #define mmPCIE_DEC0_CMD_SWREG1 0x4F00004 #define mmPCIE_DEC0_CMD_SWREG2 0x4F00008 #define mmPCIE_DEC0_CMD_SWREG3 0x4F0000C #define mmPCIE_DEC0_CMD_SWREG4 0x4F00010 #define mmPCIE_DEC0_CMD_SWREG5 0x4F00014 #define mmPCIE_DEC0_CMD_SWREG6 0x4F00018 #define mmPCIE_DEC0_CMD_SWREG7 0x4F0001C #define mmPCIE_DEC0_CMD_SWREG8 0x4F00020 #define mmPCIE_DEC0_CMD_SWREG9 0x4F00024 #define mmPCIE_DEC0_CMD_SWREG10 0x4F00028 #define mmPCIE_DEC0_CMD_SWREG11 0x4F0002C #define mmPCIE_DEC0_CMD_SWREG12 0x4F00030 #define mmPCIE_DEC0_CMD_SWREG13 0x4F00034 #define mmPCIE_DEC0_CMD_SWREG14 0x4F00038 #define mmPCIE_DEC0_CMD_SWREG15 0x4F0003C #define mmPCIE_DEC0_CMD_SWREG16 0x4F00040 #define mmPCIE_DEC0_CMD_SWREG17 0x4F00044 #define mmPCIE_DEC0_CMD_SWREG18 0x4F00048 #define mmPCIE_DEC0_CMD_SWREG19 0x4F0004C #define mmPCIE_DEC0_CMD_SWREG20 0x4F00050 #define mmPCIE_DEC0_CMD_SWREG21 0x4F00054 #define mmPCIE_DEC0_CMD_SWREG22 0x4F00058 #define mmPCIE_DEC0_CMD_SWREG23 0x4F0005C #define mmPCIE_DEC0_CMD_SWREG24 0x4F00060 #define mmPCIE_DEC0_CMD_SWREG25 0x4F00064 #define mmPCIE_DEC0_CMD_SWREG26 0x4F00068 #define mmPCIE_DEC0_CMD_SWREG64 0x4F00100 #define mmPCIE_DEC0_CMD_SWREG65 0x4F00104 #define mmPCIE_DEC0_CMD_SWREG66 0x4F00108 #define mmPCIE_DEC0_CMD_SWREG67 0x4F0010C #endif /* ASIC_REG_PCIE_DEC0_CMD_REGS_H_ */