Contributors: 1
Author Tokens Token Proportion Commits Commit Proportion
Oded Gabbay 1148 100.00% 2 100.00%
Total 1148 2 


/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_
#define ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_

/*
 *****************************************
 *   ROT0_QM_ARC_AUX
 *   (Prototype: QMAN_ARC_AUX)
 *****************************************
 */

#define mmROT0_QM_ARC_AUX_RUN_HALT_REQ 0x4E08100

#define mmROT0_QM_ARC_AUX_RUN_HALT_ACK 0x4E08104

#define mmROT0_QM_ARC_AUX_RST_VEC_ADDR 0x4E08108

#define mmROT0_QM_ARC_AUX_DBG_MODE 0x4E0810C

#define mmROT0_QM_ARC_AUX_CLUSTER_NUM 0x4E08110

#define mmROT0_QM_ARC_AUX_ARC_NUM 0x4E08114

#define mmROT0_QM_ARC_AUX_WAKE_UP_EVENT 0x4E08118

#define mmROT0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4E0811C

#define mmROT0_QM_ARC_AUX_CTI_AP_STS 0x4E08120

#define mmROT0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4E08124

#define mmROT0_QM_ARC_AUX_ARC_RST 0x4E08128

#define mmROT0_QM_ARC_AUX_ARC_RST_REQ 0x4E0812C

#define mmROT0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4E08130

#define mmROT0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4E08134

#define mmROT0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4E08138

#define mmROT0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4E0813C

#define mmROT0_QM_ARC_AUX_CFG_LSB_ADDR 0x4E08140

#define mmROT0_QM_ARC_AUX_CFG_MSB_ADDR 0x4E08144

#define mmROT0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4E08150

#define mmROT0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4E08154

#define mmROT0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4E08158

#define mmROT0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4E0815C

#define mmROT0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4E08160

#define mmROT0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4E08164

#define mmROT0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4E08168

#define mmROT0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4E0816C

#define mmROT0_QM_ARC_AUX_HBM0_OFFSET 0x4E08170

#define mmROT0_QM_ARC_AUX_HBM1_OFFSET 0x4E08174

#define mmROT0_QM_ARC_AUX_HBM2_OFFSET 0x4E08178

#define mmROT0_QM_ARC_AUX_HBM3_OFFSET 0x4E0817C

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4E08180

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4E08184

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4E08188

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4E0818C

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4E08190

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4E08194

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4E08198

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4E0819C

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4E081A0

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4E081A4

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4E081A8

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4E081AC

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4E081B0

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4E081B4

#define mmROT0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4E081B8

#define mmROT0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4E081BC

#define mmROT0_QM_ARC_AUX_CONTEXT_ID_0 0x4E081C0

#define mmROT0_QM_ARC_AUX_CONTEXT_ID_1 0x4E081C4

#define mmROT0_QM_ARC_AUX_CONTEXT_ID_2 0x4E081C8

#define mmROT0_QM_ARC_AUX_CONTEXT_ID_3 0x4E081CC

#define mmROT0_QM_ARC_AUX_CONTEXT_ID_4 0x4E081D0

#define mmROT0_QM_ARC_AUX_CONTEXT_ID_5 0x4E081D4

#define mmROT0_QM_ARC_AUX_CONTEXT_ID_6 0x4E081D8

#define mmROT0_QM_ARC_AUX_CONTEXT_ID_7 0x4E081DC

#define mmROT0_QM_ARC_AUX_CID_OFFSET_0 0x4E081E0

#define mmROT0_QM_ARC_AUX_CID_OFFSET_1 0x4E081E4

#define mmROT0_QM_ARC_AUX_CID_OFFSET_2 0x4E081E8

#define mmROT0_QM_ARC_AUX_CID_OFFSET_3 0x4E081EC

#define mmROT0_QM_ARC_AUX_CID_OFFSET_4 0x4E081F0

#define mmROT0_QM_ARC_AUX_CID_OFFSET_5 0x4E081F4

#define mmROT0_QM_ARC_AUX_CID_OFFSET_6 0x4E081F8

#define mmROT0_QM_ARC_AUX_CID_OFFSET_7 0x4E081FC

#define mmROT0_QM_ARC_AUX_SW_INTR_0 0x4E08200

#define mmROT0_QM_ARC_AUX_SW_INTR_1 0x4E08204

#define mmROT0_QM_ARC_AUX_SW_INTR_2 0x4E08208

#define mmROT0_QM_ARC_AUX_SW_INTR_3 0x4E0820C

#define mmROT0_QM_ARC_AUX_SW_INTR_4 0x4E08210

#define mmROT0_QM_ARC_AUX_SW_INTR_5 0x4E08214

#define mmROT0_QM_ARC_AUX_SW_INTR_6 0x4E08218

#define mmROT0_QM_ARC_AUX_SW_INTR_7 0x4E0821C

#define mmROT0_QM_ARC_AUX_SW_INTR_8 0x4E08220

#define mmROT0_QM_ARC_AUX_SW_INTR_9 0x4E08224

#define mmROT0_QM_ARC_AUX_SW_INTR_10 0x4E08228

#define mmROT0_QM_ARC_AUX_SW_INTR_11 0x4E0822C

#define mmROT0_QM_ARC_AUX_SW_INTR_12 0x4E08230

#define mmROT0_QM_ARC_AUX_SW_INTR_13 0x4E08234

#define mmROT0_QM_ARC_AUX_SW_INTR_14 0x4E08238

#define mmROT0_QM_ARC_AUX_SW_INTR_15 0x4E0823C

#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4E08280

#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4E08284

#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4E08290

#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4E08294

#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4E08298

#define mmROT0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4E0829C

#define mmROT0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4E082A0

#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4E082A4

#define mmROT0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4E082A8

#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4E082B0

#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4E082B4

#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4E082B8

#define mmROT0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4E082BC

#define mmROT0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4E082C0

#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4E082C4

#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4E082C8

#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4E082CC

#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4E082D0

#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4E082E0

#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4E082E4

#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4E082E8

#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4E082EC

#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4E082F0

#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4E082F4

#define mmROT0_QM_ARC_AUX_SCRATCHPAD_0 0x4E08300

#define mmROT0_QM_ARC_AUX_SCRATCHPAD_1 0x4E08304

#define mmROT0_QM_ARC_AUX_SCRATCHPAD_2 0x4E08308

#define mmROT0_QM_ARC_AUX_SCRATCHPAD_3 0x4E0830C

#define mmROT0_QM_ARC_AUX_SCRATCHPAD_4 0x4E08310

#define mmROT0_QM_ARC_AUX_SCRATCHPAD_5 0x4E08314

#define mmROT0_QM_ARC_AUX_SCRATCHPAD_6 0x4E08318

#define mmROT0_QM_ARC_AUX_SCRATCHPAD_7 0x4E0831C

#define mmROT0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4E08320

#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4E08324

#define mmROT0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4E08328

#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4E0832C

#define mmROT0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4E08330

#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4E08334

#define mmROT0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4E08338

#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4E0833C

#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4E08350

#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4E08354

#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4E08358

#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4E0835C

#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4E08360

#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4E08364

#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4E08368

#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4E0836C

#define mmROT0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4E08370

#define mmROT0_QM_ARC_AUX_CBU_LOCK_OVR 0x4E08374

#define mmROT0_QM_ARC_AUX_CBU_PROT_OVR 0x4E08378

#define mmROT0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4E0837C

#define mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4E08380

#define mmROT0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4E08384

#define mmROT0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4E0838C

#define mmROT0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4E08390

#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4E08400

#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4E08404

#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4E08408

#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4E0840C

#define mmROT0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4E08420

#define mmROT0_QM_ARC_AUX_LBU_LOCK_OVR 0x4E08424

#define mmROT0_QM_ARC_AUX_LBU_PROT_OVR 0x4E08428

#define mmROT0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4E0842C

#define mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4E08430

#define mmROT0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4E08434

#define mmROT0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4E0843C

#define mmROT0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4E08440

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4E08500

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4E08504

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4E08508

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4E0850C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4E08510

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4E08514

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4E08518

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4E0851C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4E08520

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4E08524

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4E08528

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4E0852C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4E08530

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4E08534

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4E08538

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4E0853C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4E08540

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4E08544

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4E08548

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4E0854C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4E08550

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4E08554

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4E08558

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4E0855C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4E08560

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4E08564

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4E08568

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4E0856C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4E08570

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4E08574

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4E08578

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4E0857C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4E08580

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4E08584

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4E08588

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4E0858C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4E08590

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4E08594

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4E08598

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4E0859C

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4E085A0

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4E085A4

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4E085A8

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4E085AC

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4E085B0

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4E085B4

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4E085B8

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4E085BC

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4E085C0

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4E085C4

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4E085C8

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4E085CC

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4E085D0

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4E085D4

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4E085D8

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4E085DC

#define mmROT0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4E085E0

#define mmROT0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4E085E4

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4E08620

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4E08624

#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4E08628

#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4E08630

#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4E08634

#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4E08638

#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4E0863C

#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4E08640

#define mmROT0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4E08644

#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4E08648

#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4E0864C

#define mmROT0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4E08650

#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4E08654

#define mmROT0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4E08658

#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4E0865C

#define mmROT0_QM_ARC_AUX_AUX2APB_PROT 0x4E08700

#define mmROT0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4E08704

#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4E08708

#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4E0870C

#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4E08710

#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4E08714

#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4E08718

#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4E0871C

#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4E08720

#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4E08724

#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4E08728

#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4E0872C

#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4E08730

#define mmROT0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4E08734

#define mmROT0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4E08738

#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4E0873C

#define mmROT0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4E08740

#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4E08750

#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4E08754

#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4E08758

#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4E0875C

#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4E08760

#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4E08764

#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4E08768

#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4E0876C

#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4E08770

#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4E08774

#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4E08778

#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4E0877C

#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4E08780

#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4E08784

#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4E08788

#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4E0878C

#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4E08790

#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4E08794

#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4E08798

#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4E0879C

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4E08800

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4E08804

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4E08808

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4E0880C

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4E08810

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4E08814

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4E08818

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4E0881C

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4E08820

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4E08824

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4E08828

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4E0882C

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4E08830

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4E08834

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4E08838

#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4E0883C

#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4E08840

#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4E08844

#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4E08848

#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4E0884C

#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4E08850

#define mmROT0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4E08854

#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4E08900

#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4E08904

#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4E08908

#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4E0890C

#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4E08910

#define mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4E08920

#endif /* ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_ */