Contributors: 9
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Chris Wilson |
127 |
63.18% |
16 |
59.26% |
| Xiang, Haihao |
31 |
15.42% |
1 |
3.70% |
| Paulo Zanoni |
18 |
8.96% |
1 |
3.70% |
| Michal Wajdeczko |
7 |
3.48% |
2 |
7.41% |
| Tvrtko A. Ursulin |
7 |
3.48% |
3 |
11.11% |
| Zou Nan hai |
6 |
2.99% |
1 |
3.70% |
| Ben Widawsky |
2 |
1.00% |
1 |
3.70% |
| John Harrison |
2 |
1.00% |
1 |
3.70% |
| Jonathan Gray |
1 |
0.50% |
1 |
3.70% |
| Total |
201 |
|
27 |
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2020 Intel Corporation
*/
#ifndef __GEN6_ENGINE_CS_H__
#define __GEN6_ENGINE_CS_H__
#include <linux/types.h>
#include "intel_gpu_commands.h"
struct i915_request;
struct intel_engine_cs;
int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode);
int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode);
int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode);
u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode);
u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
int gen6_emit_bb_start(struct i915_request *rq,
u64 offset, u32 len,
unsigned int dispatch_flags);
int hsw_emit_bb_start(struct i915_request *rq,
u64 offset, u32 len,
unsigned int dispatch_flags);
void gen6_irq_enable(struct intel_engine_cs *engine);
void gen6_irq_disable(struct intel_engine_cs *engine);
void hsw_irq_enable_vecs(struct intel_engine_cs *engine);
void hsw_irq_disable_vecs(struct intel_engine_cs *engine);
#endif /* __GEN6_ENGINE_CS_H__ */