Contributors: 23
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Venkatesh Pallipadi |
131 |
26.73% |
1 |
2.94% |
| Fenghua Yu |
96 |
19.59% |
4 |
11.76% |
| H. Peter Anvin |
28 |
5.71% |
1 |
2.94% |
| Sandipan Das |
24 |
4.90% |
2 |
5.88% |
| Sean Christopherson |
24 |
4.90% |
1 |
2.94% |
| Babu Moger |
24 |
4.90% |
2 |
5.88% |
| Suresh B. Siddha |
18 |
3.67% |
2 |
5.88% |
| He Chen |
16 |
3.27% |
2 |
5.88% |
| Borislav Petkov |
13 |
2.65% |
2 |
5.88% |
| Sherry Hurwitz |
13 |
2.65% |
1 |
2.94% |
| Pawan Gupta |
12 |
2.45% |
1 |
2.94% |
| Kai Huang |
12 |
2.45% |
1 |
2.94% |
| Vikas Shivappa |
12 |
2.45% |
1 |
2.94% |
| Tony Luck |
12 |
2.45% |
1 |
2.94% |
| Andi Kleen |
11 |
2.24% |
2 |
5.88% |
| Thomas Renninger |
11 |
2.24% |
1 |
2.94% |
| Piotr Luc |
10 |
2.04% |
1 |
2.94% |
| Alexander Shishkin |
8 |
1.63% |
1 |
2.94% |
| Thomas Gleixner |
5 |
1.02% |
2 |
5.88% |
| Jacob Shin |
4 |
0.82% |
1 |
2.94% |
| Jeremy Fitzhardinge |
3 |
0.61% |
1 |
2.94% |
| Ingo Molnar |
2 |
0.41% |
2 |
5.88% |
| Maxime Jayat |
1 |
0.20% |
1 |
2.94% |
| Total |
490 |
|
34 |
|
/*
* Routines to identify additional cpu features that are scattered in
* cpuid space.
*/
#include <linux/cpu.h>
#include <asm/memtype.h>
#include <asm/apic.h>
#include <asm/processor.h>
#include "cpu.h"
struct cpuid_bit {
u16 feature;
u8 reg;
u8 bit;
u32 level;
u32 sub_leaf;
};
/*
* Please keep the leaf sorted by cpuid_bit.level for faster search.
* X86_FEATURE_MBA is supported by both Intel and AMD. But the CPUID
* levels are different and there is a separate entry for each.
*/
static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
{ X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
{ X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 },
{ X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 },
{ X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
{ X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
{ X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
{ X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 },
{ X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
{ X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
{ X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 },
{ X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
{ X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 },
{ X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 },
{ X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 },
{ X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 },
{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
{ X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },
{ X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },
{ X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
{ X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 },
{ 0, 0, 0, 0, 0 }
};
void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
{
u32 max_level;
u32 regs[4];
const struct cpuid_bit *cb;
for (cb = cpuid_bits; cb->feature; cb++) {
/* Verify that the level is valid */
max_level = cpuid_eax(cb->level & 0xffff0000);
if (max_level < cb->level ||
max_level > (cb->level | 0xffff))
continue;
cpuid_count(cb->level, cb->sub_leaf, ®s[CPUID_EAX],
®s[CPUID_EBX], ®s[CPUID_ECX],
®s[CPUID_EDX]);
if (regs[cb->reg] & (1 << cb->bit))
set_cpu_cap(c, cb->feature);
}
}