/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "../dmub_srv.h" #include "dmub_reg.h" #include "dmub_dcn315.h" #include "dcn/dcn_3_1_5_offset.h" #include "dcn/dcn_3_1_5_sh_mask.h" #define DCN_BASE__INST0_SEG0 0x00000012 #define DCN_BASE__INST0_SEG1 0x000000C0 #define DCN_BASE__INST0_SEG2 0x000034C0 #define DCN_BASE__INST0_SEG3 0x00009000 #define DCN_BASE__INST0_SEG4 0x02403C00 #define DCN_BASE__INST0_SEG5 0 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg #define CTX dmub #define REGS dmub->regs_dcn31 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) /* Registers. */ const struct dmub_srv_dcn31_regs dmub_srv_dcn315_regs = { #define DMUB_SR(reg) REG_OFFSET_EXP(reg), { DMUB_DCN31_REGS() DMCUB_INTERNAL_REGS() }, #undef DMUB_SR #define DMUB_SF(reg, field) FD_MASK(reg, field), { DMUB_DCN315_FIELDS() }, #undef DMUB_SF #define DMUB_SF(reg, field) FD_SHIFT(reg, field), { DMUB_DCN315_FIELDS() }, #undef DMUB_SF };