Contributors: 12
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Jani Nikula |
85 |
40.28% |
5 |
17.86% |
| Ville Syrjälä |
45 |
21.33% |
7 |
25.00% |
| Paulo Zanoni |
35 |
16.59% |
4 |
14.29% |
| Imre Deak |
10 |
4.74% |
2 |
7.14% |
| Rodrigo Vivi |
10 |
4.74% |
1 |
3.57% |
| Daniel Vetter |
9 |
4.27% |
2 |
7.14% |
| Ander Conselvan de Oliveira |
7 |
3.32% |
2 |
7.14% |
| Ramalingam C |
3 |
1.42% |
1 |
3.57% |
| Clint Taylor |
2 |
0.95% |
1 |
3.57% |
| Matt Roper |
2 |
0.95% |
1 |
3.57% |
| Ankit Nautiyal |
2 |
0.95% |
1 |
3.57% |
| Chris Wilson |
1 |
0.47% |
1 |
3.57% |
| Total |
211 |
|
28 |
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2020 Intel Corporation
*/
#ifndef _G4X_DP_H_
#define _G4X_DP_H_
#include <linux/types.h>
#include "i915_reg_defs.h"
enum pipe;
enum port;
struct drm_i915_private;
struct intel_crtc_state;
struct intel_dp;
struct intel_encoder;
#ifdef I915
const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
enum pipe vlv_active_pipe(struct intel_dp *intel_dp);
void g4x_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
i915_reg_t dp_reg, enum port port,
enum pipe *pipe);
bool g4x_dp_init(struct drm_i915_private *dev_priv,
i915_reg_t output_reg, enum port port);
#else
static inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
{
return NULL;
}
static inline int vlv_active_pipe(struct intel_dp *intel_dp)
{
return 0;
}
static inline void g4x_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
}
static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
i915_reg_t dp_reg, int port,
enum pipe *pipe)
{
return false;
}
static inline bool g4x_dp_init(struct drm_i915_private *dev_priv,
i915_reg_t output_reg, int port)
{
return false;
}
#endif
#endif