Contributors: 17
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Radhakrishna Sripada |
88 |
34.51% |
2 |
4.17% |
| Mika Kahola |
39 |
15.29% |
8 |
16.67% |
| Ville Syrjälä |
30 |
11.76% |
10 |
20.83% |
| Paulo Zanoni |
26 |
10.20% |
3 |
6.25% |
| Jani Nikula |
18 |
7.06% |
5 |
10.42% |
| Maarten Lankhorst |
10 |
3.92% |
2 |
4.17% |
| Shashank Sharma |
8 |
3.14% |
1 |
2.08% |
| Ander Conselvan de Oliveira |
7 |
2.75% |
4 |
8.33% |
| Dave Airlie |
6 |
2.35% |
2 |
4.17% |
| José Roberto de Souza |
5 |
1.96% |
2 |
4.17% |
| Daniel Vetter |
4 |
1.57% |
2 |
4.17% |
| Chris Wilson |
4 |
1.57% |
2 |
4.17% |
| Zhenyu Wang |
3 |
1.18% |
1 |
2.08% |
| Keith Packard |
3 |
1.18% |
1 |
2.08% |
| Jesse Barnes |
2 |
0.78% |
1 |
2.08% |
| Eric Anholt |
1 |
0.39% |
1 |
2.08% |
| Imre Deak |
1 |
0.39% |
1 |
2.08% |
| Total |
255 |
|
48 |
|
// SPDX-License-Identifier: MIT
/*
* Copyright © 2023 Intel Corporation
*/
#ifndef __INTEL_CX0_PHY_H__
#define __INTEL_CX0_PHY_H__
#include <linux/types.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
enum icl_port_dpll_id;
enum phy;
struct drm_i915_private;
struct intel_atomic_state;
struct intel_c10pll_state;
struct intel_c20pll_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdmi;
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_disable(struct intel_encoder *encoder);
enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c10pll_state *pll_state);
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_c10pll_state *hw_state);
int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10pll_state *pll_state);
void intel_c10pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state);
void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
const struct intel_c20pll_state *hw_state);
int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c20pll_state *pll_state);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
#endif /* __INTEL_CX0_PHY_H__ */