Contributors: 14
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Vinay Belgaumkar |
210 |
68.85% |
2 |
6.67% |
| Michal Wajdeczko |
26 |
8.52% |
6 |
20.00% |
| Matthew Brost |
18 |
5.90% |
4 |
13.33% |
| Arkadiusz Hiler |
12 |
3.93% |
2 |
6.67% |
| John Harrison |
8 |
2.62% |
1 |
3.33% |
| Daniele Ceraolo Spurio |
7 |
2.30% |
3 |
10.00% |
| Lucas De Marchi |
5 |
1.64% |
3 |
10.00% |
| Badal Nilawar |
4 |
1.31% |
1 |
3.33% |
| Chris Wilson |
3 |
0.98% |
2 |
6.67% |
| Alex Dai |
3 |
0.98% |
1 |
3.33% |
| Sagar Arun Kamble |
3 |
0.98% |
1 |
3.33% |
| Oscar Mateo |
3 |
0.98% |
1 |
3.33% |
| Jani Nikula |
2 |
0.66% |
2 |
6.67% |
| Maarten Lankhorst |
1 |
0.33% |
1 |
3.33% |
| Total |
305 |
|
30 |
|
// SPDX-License-Identifier: MIT
/*
* Copyright © 2021 Intel Corporation
*/
#include <linux/string_helpers.h>
#include "intel_guc_rc.h"
#include "intel_guc_print.h"
#include "gt/intel_gt.h"
#include "i915_drv.h"
static bool __guc_rc_supported(struct intel_guc *guc)
{
/* GuC RC is unavailable for pre-Gen12 */
return guc->submission_supported &&
GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
}
static bool __guc_rc_selected(struct intel_guc *guc)
{
if (!intel_guc_rc_is_supported(guc))
return false;
return guc->submission_selected;
}
void intel_guc_rc_init_early(struct intel_guc *guc)
{
guc->rc_supported = __guc_rc_supported(guc);
guc->rc_selected = __guc_rc_selected(guc);
}
static int guc_action_control_gucrc(struct intel_guc *guc, bool enable)
{
u32 rc_mode = enable ? INTEL_GUCRC_FIRMWARE_CONTROL :
INTEL_GUCRC_HOST_CONTROL;
u32 action[] = {
INTEL_GUC_ACTION_SETUP_PC_GUCRC,
rc_mode
};
int ret;
ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
ret = ret > 0 ? -EPROTO : ret;
return ret;
}
static int __guc_rc_control(struct intel_guc *guc, bool enable)
{
struct intel_gt *gt = guc_to_gt(guc);
int ret;
if (!intel_uc_uses_guc_rc(>->uc))
return -EOPNOTSUPP;
if (!intel_guc_is_ready(guc))
return -EINVAL;
ret = guc_action_control_gucrc(guc, enable);
if (ret) {
guc_probe_error(guc, "Failed to %s RC (%pe)\n",
str_enable_disable(enable), ERR_PTR(ret));
return ret;
}
guc_info(guc, "RC %s\n", str_enabled_disabled(enable));
return 0;
}
int intel_guc_rc_enable(struct intel_guc *guc)
{
return __guc_rc_control(guc, true);
}
int intel_guc_rc_disable(struct intel_guc *guc)
{
return __guc_rc_control(guc, false);
}