/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2023 MediaTek Inc. * Author: Balsam CHIHI <bchihi@baylibre.com> */ #ifndef __MEDIATEK_LVTS_DT_H #define __MEDIATEK_LVTS_DT_H #define MT7988_CPU_0 0 #define MT7988_CPU_1 1 #define MT7988_ETH2P5G_0 2 #define MT7988_ETH2P5G_1 3 #define MT7988_TOPS_0 4 #define MT7988_TOPS_1 5 #define MT7988_ETHWARP_0 6 #define MT7988_ETHWARP_1 7 #define MT8195_MCU_BIG_CPU0 0 #define MT8195_MCU_BIG_CPU1 1 #define MT8195_MCU_BIG_CPU2 2 #define MT8195_MCU_BIG_CPU3 3 #define MT8195_MCU_LITTLE_CPU0 4 #define MT8195_MCU_LITTLE_CPU1 5 #define MT8195_MCU_LITTLE_CPU2 6 #define MT8195_MCU_LITTLE_CPU3 7 #define MT8195_AP_VPU0 8 #define MT8195_AP_VPU1 9 #define MT8195_AP_GPU0 10 #define MT8195_AP_GPU1 11 #define MT8195_AP_VDEC 12 #define MT8195_AP_IMG 13 #define MT8195_AP_INFRA 14 #define MT8195_AP_CAM0 15 #define MT8195_AP_CAM1 16 #define MT8192_MCU_BIG_CPU0 0 #define MT8192_MCU_BIG_CPU1 1 #define MT8192_MCU_BIG_CPU2 2 #define MT8192_MCU_BIG_CPU3 3 #define MT8192_MCU_LITTLE_CPU0 4 #define MT8192_MCU_LITTLE_CPU1 5 #define MT8192_MCU_LITTLE_CPU2 6 #define MT8192_MCU_LITTLE_CPU3 7 #define MT8192_AP_VPU0 8 #define MT8192_AP_VPU1 9 #define MT8192_AP_GPU0 10 #define MT8192_AP_GPU1 11 #define MT8192_AP_INFRA 12 #define MT8192_AP_CAM 13 #define MT8192_AP_MD0 14 #define MT8192_AP_MD1 15 #define MT8192_AP_MD2 16 #endif /* __MEDIATEK_LVTS_DT_H */