/* SPDX-License-Identifier: GPL-2.0 */ /* * mt8188-audsys-clkid.h -- MediaTek 8188 audsys clock id definition * * Copyright (c) 2022 MediaTek Inc. * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com> */ #ifndef _MT8188_AUDSYS_CLKID_H_ #define _MT8188_AUDSYS_CLKID_H_ enum{ CLK_AUD_AFE, CLK_AUD_LRCK_CNT, CLK_AUD_SPDIFIN_TUNER_APLL, CLK_AUD_SPDIFIN_TUNER_DBG, CLK_AUD_UL_TML, CLK_AUD_APLL1_TUNER, CLK_AUD_APLL2_TUNER, CLK_AUD_TOP0_SPDF, CLK_AUD_APLL, CLK_AUD_APLL2, CLK_AUD_DAC, CLK_AUD_DAC_PREDIS, CLK_AUD_TML, CLK_AUD_ADC, CLK_AUD_DAC_HIRES, CLK_AUD_A1SYS_HP, CLK_AUD_AFE_DMIC1, CLK_AUD_AFE_DMIC2, CLK_AUD_AFE_DMIC3, CLK_AUD_AFE_DMIC4, CLK_AUD_AFE_26M_DMIC_TM, CLK_AUD_UL_TML_HIRES, CLK_AUD_ADC_HIRES, CLK_AUD_LINEIN_TUNER, CLK_AUD_EARC_TUNER, CLK_AUD_I2SIN, CLK_AUD_TDM_IN, CLK_AUD_I2S_OUT, CLK_AUD_TDM_OUT, CLK_AUD_HDMI_OUT, CLK_AUD_ASRC11, CLK_AUD_ASRC12, CLK_AUD_MULTI_IN, CLK_AUD_INTDIR, CLK_AUD_A1SYS, CLK_AUD_A2SYS, CLK_AUD_PCMIF, CLK_AUD_A3SYS, CLK_AUD_A4SYS, CLK_AUD_MEMIF_UL1, CLK_AUD_MEMIF_UL2, CLK_AUD_MEMIF_UL3, CLK_AUD_MEMIF_UL4, CLK_AUD_MEMIF_UL5, CLK_AUD_MEMIF_UL6, CLK_AUD_MEMIF_UL8, CLK_AUD_MEMIF_UL9, CLK_AUD_MEMIF_UL10, CLK_AUD_MEMIF_DL2, CLK_AUD_MEMIF_DL3, CLK_AUD_MEMIF_DL6, CLK_AUD_MEMIF_DL7, CLK_AUD_MEMIF_DL8, CLK_AUD_MEMIF_DL10, CLK_AUD_MEMIF_DL11, CLK_AUD_GASRC0, CLK_AUD_GASRC1, CLK_AUD_GASRC2, CLK_AUD_GASRC3, CLK_AUD_GASRC4, CLK_AUD_GASRC5, CLK_AUD_GASRC6, CLK_AUD_GASRC7, CLK_AUD_GASRC8, CLK_AUD_GASRC9, CLK_AUD_GASRC10, CLK_AUD_GASRC11, CLK_AUD_NR_CLK, }; #endif