Contributors: 14
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Radhakrishna Sripada |
83 |
36.24% |
2 |
5.26% |
| Mika Kahola |
33 |
14.41% |
8 |
21.05% |
| Lucas De Marchi |
26 |
11.35% |
2 |
5.26% |
| Paulo Zanoni |
22 |
9.61% |
3 |
7.89% |
| Jani Nikula |
18 |
7.86% |
5 |
13.16% |
| Ville Syrjälä |
15 |
6.55% |
6 |
15.79% |
| Maarten Lankhorst |
10 |
4.37% |
2 |
5.26% |
| Ander Conselvan de Oliveira |
9 |
3.93% |
3 |
7.89% |
| Shashank Sharma |
4 |
1.75% |
1 |
2.63% |
| Daniel Vetter |
3 |
1.31% |
2 |
5.26% |
| Imre Deak |
2 |
0.87% |
1 |
2.63% |
| Chris Wilson |
2 |
0.87% |
1 |
2.63% |
| José Roberto de Souza |
1 |
0.44% |
1 |
2.63% |
| Dave Airlie |
1 |
0.44% |
1 |
2.63% |
| Total |
229 |
|
38 |
|
// SPDX-License-Identifier: MIT
/*
* Copyright © 2023 Intel Corporation
*/
#ifndef __INTEL_CX0_PHY_H__
#define __INTEL_CX0_PHY_H__
#include <linux/types.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
enum icl_port_dpll_id;
enum phy;
struct drm_i915_private;
struct intel_atomic_state;
struct intel_c10pll_state;
struct intel_c20pll_state;
struct intel_cx0pll_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdmi;
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_pll_disable(struct intel_encoder *encoder);
enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_cx0pll_state *pll_state);
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_cx0pll_state *pll_state);
void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_c10pll_state *hw_state);
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
const struct intel_c20pll_state *hw_state);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
#endif /* __INTEL_CX0_PHY_H__ */