Contributors: 29
Author Tokens Token Proportion Commits Commit Proportion
Dave Jones 85 20.38% 2 4.44%
Linus Torvalds (pre-git) 65 15.59% 1 2.22%
Pawan Gupta 57 13.67% 4 8.89%
Borislav Petkov 35 8.39% 4 8.89%
Alex Shi 29 6.95% 1 2.22%
Jan Beulich 26 6.24% 2 4.44%
Thomas Petazzoni 18 4.32% 1 2.22%
Yinghai Lu 17 4.08% 3 6.67%
Thomas Gleixner 15 3.60% 6 13.33%
Linus Torvalds 8 1.92% 1 2.22%
Andi Kleen 8 1.92% 2 4.44%
David Woodhouse 8 1.92% 1 2.22%
Konrad Rzeszutek Wilk 5 1.20% 1 2.22%
M. Vefa Bicakci 5 1.20% 1 2.22%
H. Peter Anvin 5 1.20% 1 2.22%
Rafael J. Wysocki 4 0.96% 1 2.22%
Daniel Sneddon 3 0.72% 1 2.22%
Pu Wen 3 0.72% 1 2.22%
Venkatesh Pallipadi 3 0.72% 1 2.22%
Peter Zijlstra 3 0.72% 1 2.22%
Mark Gross 3 0.72% 1 2.22%
Jane Malalane 3 0.72% 1 2.22%
Robert Richter 2 0.48% 1 2.22%
Suravee Suthikulpanit 2 0.48% 1 2.22%
Joe Perches 1 0.24% 1 2.22%
Greg Kroah-Hartman 1 0.24% 1 2.22%
David Wang 1 0.24% 1 2.22%
Viresh Kumar 1 0.24% 1 2.22%
Jaswinder Singh Rajput 1 0.24% 1 2.22%
Total 417 45 


/* SPDX-License-Identifier: GPL-2.0 */
#ifndef ARCH_X86_CPU_H
#define ARCH_X86_CPU_H

#include <asm/cpu.h>
#include <asm/topology.h>

#include "topology.h"

/* attempt to consolidate cpu attributes */
struct cpu_dev {
	const char	*c_vendor;

	/* some have two possibilities for cpuid string */
	const char	*c_ident[2];

	void            (*c_early_init)(struct cpuinfo_x86 *);
	void		(*c_bsp_init)(struct cpuinfo_x86 *);
	void		(*c_init)(struct cpuinfo_x86 *);
	void		(*c_identify)(struct cpuinfo_x86 *);
	void		(*c_detect_tlb)(struct cpuinfo_x86 *);
	int		c_x86_vendor;
#ifdef CONFIG_X86_32
	/* Optional vendor specific routine to obtain the cache size. */
	unsigned int	(*legacy_cache_size)(struct cpuinfo_x86 *,
					     unsigned int);

	/* Family/stepping-based lookup table for model names. */
	struct legacy_cpu_model_info {
		int		family;
		const char	*model_names[16];
	}		legacy_models[5];
#endif
};

struct _tlb_table {
	unsigned char descriptor;
	char tlb_type;
	unsigned int entries;
	/* unsigned int ways; */
	char info[128];
};

#define cpu_dev_register(cpu_devX) \
	static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
	__section(".x86_cpu_dev.init") = \
	&cpu_devX;

extern const struct cpu_dev *const __x86_cpu_dev_start[],
			    *const __x86_cpu_dev_end[];

#ifdef CONFIG_CPU_SUP_INTEL
enum tsx_ctrl_states {
	TSX_CTRL_ENABLE,
	TSX_CTRL_DISABLE,
	TSX_CTRL_RTM_ALWAYS_ABORT,
	TSX_CTRL_NOT_SUPPORTED,
};

extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;

extern void __init tsx_init(void);
void tsx_ap_init(void);
#else
static inline void tsx_init(void) { }
static inline void tsx_ap_init(void) { }
#endif /* CONFIG_CPU_SUP_INTEL */

extern void init_spectral_chicken(struct cpuinfo_x86 *c);

extern void get_cpu_cap(struct cpuinfo_x86 *c);
extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);

extern void check_null_seg_clears_base(struct cpuinfo_x86 *c);

void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id);
void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c);

unsigned int aperfmperf_get_khz(int cpu);
void cpu_select_mitigations(void);

extern void x86_spec_ctrl_setup_ap(void);
extern void update_srbds_msr(void);
extern void update_gds_msr(void);

extern enum spectre_v2_mitigation spectre_v2_enabled;

static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
{
	return mode == SPECTRE_V2_EIBRS ||
	       mode == SPECTRE_V2_EIBRS_RETPOLINE ||
	       mode == SPECTRE_V2_EIBRS_LFENCE;
}

#endif /* ARCH_X86_CPU_H */