/* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2019 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ #include <dt-bindings/clock/renesas-cpg-mssr.h> /* r8a774b1 CPG Core Clocks */ #define R8A774B1_CLK_Z 0 #define R8A774B1_CLK_ZG 1 #define R8A774B1_CLK_ZTR 2 #define R8A774B1_CLK_ZTRD2 3 #define R8A774B1_CLK_ZT 4 #define R8A774B1_CLK_ZX 5 #define R8A774B1_CLK_S0D1 6 #define R8A774B1_CLK_S0D2 7 #define R8A774B1_CLK_S0D3 8 #define R8A774B1_CLK_S0D4 9 #define R8A774B1_CLK_S0D6 10 #define R8A774B1_CLK_S0D8 11 #define R8A774B1_CLK_S0D12 12 #define R8A774B1_CLK_S1D2 13 #define R8A774B1_CLK_S1D4 14 #define R8A774B1_CLK_S2D1 15 #define R8A774B1_CLK_S2D2 16 #define R8A774B1_CLK_S2D4 17 #define R8A774B1_CLK_S3D1 18 #define R8A774B1_CLK_S3D2 19 #define R8A774B1_CLK_S3D4 20 #define R8A774B1_CLK_LB 21 #define R8A774B1_CLK_CL 22 #define R8A774B1_CLK_ZB3 23 #define R8A774B1_CLK_ZB3D2 24 #define R8A774B1_CLK_CR 25 #define R8A774B1_CLK_DDR 26 #define R8A774B1_CLK_SD0H 27 #define R8A774B1_CLK_SD0 28 #define R8A774B1_CLK_SD1H 29 #define R8A774B1_CLK_SD1 30 #define R8A774B1_CLK_SD2H 31 #define R8A774B1_CLK_SD2 32 #define R8A774B1_CLK_SD3H 33 #define R8A774B1_CLK_SD3 34 #define R8A774B1_CLK_RPC 35 #define R8A774B1_CLK_RPCD2 36 #define R8A774B1_CLK_MSO 37 #define R8A774B1_CLK_HDMI 38 #define R8A774B1_CLK_CSI0 39 #define R8A774B1_CLK_CP 40 #define R8A774B1_CLK_CPEX 41 #define R8A774B1_CLK_R 42 #define R8A774B1_CLK_OSC 43 #define R8A774B1_CLK_CANFD 44 #endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */