/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ /* * Copyright (c) 2022 MediaTek Inc. * Author: Sam Shih <sam.shih@mediatek.com> */ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 #define _DT_BINDINGS_RESET_CONTROLLER_MT7986 /* INFRACFG resets */ #define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6 #define MT7986_INFRACFG_SSUSB_SW_RST 7 #define MT7986_INFRACFG_EIP97_SW_RST 8 #define MT7986_INFRACFG_AUDIO_SW_RST 13 #define MT7986_INFRACFG_CQ_DMA_SW_RST 14 #define MT7986_INFRACFG_TRNG_SW_RST 17 #define MT7986_INFRACFG_AP_DMA_SW_RST 32 #define MT7986_INFRACFG_I2C_SW_RST 33 #define MT7986_INFRACFG_NFI_SW_RST 34 #define MT7986_INFRACFG_SPI0_SW_RST 35 #define MT7986_INFRACFG_SPI1_SW_RST 36 #define MT7986_INFRACFG_UART0_SW_RST 37 #define MT7986_INFRACFG_UART1_SW_RST 38 #define MT7986_INFRACFG_UART2_SW_RST 39 #define MT7986_INFRACFG_AUXADC_SW_RST 43 #define MT7986_INFRACFG_APXGPT_SW_RST 66 #define MT7986_INFRACFG_PWM_SW_RST 68 #define MT7986_INFRACFG_SW_RST_NUM 69 /* TOPRGU resets */ #define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0 #define MT7986_TOPRGU_SGMII0_SW_RST 1 #define MT7986_TOPRGU_SGMII1_SW_RST 2 #define MT7986_TOPRGU_INFRA_SW_RST 3 #define MT7986_TOPRGU_U2PHY_SW_RST 5 #define MT7986_TOPRGU_PCIE_SW_RST 6 #define MT7986_TOPRGU_SSUSB_SW_RST 7 #define MT7986_TOPRGU_ETHDMA_SW_RST 20 #define MT7986_TOPRGU_CONSYS_SW_RST 23 #define MT7986_TOPRGU_SW_RST_NUM 24 /* ETHSYS Subsystem resets */ #define MT7986_ETHSYS_FE_SW_RST 6 #define MT7986_ETHSYS_PMTR_SW_RST 8 #define MT7986_ETHSYS_GMAC_SW_RST 23 #define MT7986_ETHSYS_PPE0_SW_RST 30 #define MT7986_ETHSYS_PPE1_SW_RST 31 #define MT7986_ETHSYS_SW_RST_NUM 32 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */