Contributors: 13
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Will Deacon |
47 |
24.23% |
2 |
8.33% |
| Catalin Marinas |
38 |
19.59% |
3 |
12.50% |
| Christoph Hellwig |
31 |
15.98% |
6 |
25.00% |
| Masayoshi Mizuma |
21 |
10.82% |
1 |
4.17% |
| Robin Murphy |
17 |
8.76% |
3 |
12.50% |
| Suravee Suthikulpanit |
16 |
8.25% |
1 |
4.17% |
| Linus Torvalds |
7 |
3.61% |
1 |
4.17% |
| Stefano Stabellini |
5 |
2.58% |
2 |
8.33% |
| Oleksandr Tyshchenko |
5 |
2.58% |
1 |
4.17% |
| JiSheng Zhang |
3 |
1.55% |
1 |
4.17% |
| Barry Song |
2 |
1.03% |
1 |
4.17% |
| Thomas Gleixner |
1 |
0.52% |
1 |
4.17% |
| Geert Uytterhoeven |
1 |
0.52% |
1 |
4.17% |
| Total |
194 |
|
24 |
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 ARM Ltd.
* Author: Catalin Marinas <catalin.marinas@arm.com>
*/
#include <linux/gfp.h>
#include <linux/cache.h>
#include <linux/dma-map-ops.h>
#include <xen/xen.h>
#include <asm/cacheflush.h>
#include <asm/xen/xen-ops.h>
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
enum dma_data_direction dir)
{
unsigned long start = (unsigned long)phys_to_virt(paddr);
dcache_clean_poc_nosync(start, start + size);
}
void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
enum dma_data_direction dir)
{
unsigned long start = (unsigned long)phys_to_virt(paddr);
if (dir == DMA_TO_DEVICE)
return;
dcache_inval_poc_nosync(start, start + size);
}
void arch_dma_prep_coherent(struct page *page, size_t size)
{
unsigned long start = (unsigned long)page_address(page);
dcache_clean_poc(start, start + size);
}
void arch_setup_dma_ops(struct device *dev, bool coherent)
{
int cls = cache_line_size_of_cpu();
WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN,
TAINT_CPU_OUT_OF_SPEC,
"%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
dev_driver_string(dev), dev_name(dev),
ARCH_DMA_MINALIGN, cls);
dev->dma_coherent = coherent;
xen_setup_dma_ops(dev);
}