Contributors: 9
Author Tokens Token Proportion Commits Commit Proportion
Yongqiang Sun 290 70.56% 2 15.38%
Ivan Lipski 57 13.87% 2 15.38%
Bhuvana Chandra Pinninti 22 5.35% 1 7.69%
Bhawanpreet Lakha 16 3.89% 2 15.38%
Wesley Chalmers 15 3.65% 2 15.38%
Harry Wentland 8 1.95% 1 7.69%
Dmytro Laktyushkin 1 0.24% 1 7.69%
Kees Cook 1 0.24% 1 7.69%
rodrigosiqueira 1 0.24% 1 7.69%
Total 411 13 


/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "reg_helper.h"
#include "core_types.h"
#include "dcn20/dcn20_dccg.h"
#include "dcn21_dccg.h"

#define TO_DCN_DCCG(dccg)\
	container_of(dccg, struct dcn_dccg, base)

#define REG(reg) \
	(dccg_dcn->regs->reg)

#undef FN
#define FN(reg_name, field_name) \
	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

#define CTX \
	dccg_dcn->base.ctx
#define DC_LOGGER \
	dccg->ctx->logger

static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
{
	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

	if (dccg->ref_dppclk) {
		int ref_dppclk = dccg->ref_dppclk;
		int modulo = ref_dppclk / 10000;
		int phase;

		if (req_dppclk) {
			/*
			 * program DPP DTO phase and modulo as below
			 * phase = ceiling(dpp_pipe_clk_mhz / 10)
			 * module = trunc(dpp_global_clk_mhz / 10)
			 *
			 * storing frequencies in registers allow dmcub fw
			 * to run time lower clocks when possible for power saving
			 *
			 * ceiling phase and truncate modulo guarentees the divided
			 * down per pipe dpp clock has high enough frequency
			 */
			phase = (req_dppclk + 9999) / 10000;

			if (phase > modulo) {
				/* phase > modulo result in screen corruption
				 * ie phase = 30, mod = 29 for 4k@60 HDMI
				 * in these case we don't want pipe clock to be divided
				 */
				phase = modulo;
			}
		} else {
			/*
			 *  set phase to 10 if dpp isn't used to
			 *  prevent hard hang if access dpp register
			 *  on unused pipe
			 *
			 *  DTO should be on to divide down un-used
			 *  pipe clock for power saving
			 */
			phase = 10;
		}

		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
				DPPCLK0_DTO_PHASE, phase,
				DPPCLK0_DTO_MODULO, modulo);

		REG_UPDATE(DPPCLK_DTO_CTRL,
				DPPCLK_DTO_ENABLE[dpp_inst], 1);
	}

	dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
}

/*
 * On DCN21 S0i3 resume, BIOS programs MICROSECOND_TIME_BASE_DIV to
 * 0x00120464 as a marker that golden init has already been done.
 * dcn21_s0i3_golden_init_wa() reads this marker later in bios_golden_init()
 * to decide whether to skip golden init.
 *
 * dccg2_init() unconditionally overwrites MICROSECOND_TIME_BASE_DIV to
 * 0x00120264, destroying the marker before it can be read.
 *
 * Guard the call: if the S0i3 marker is present, skip init so the
 * WA can function correctly. bios_golden_init() will handle init in that case.
 *
 * DCN21 uses 48MHz refclk, not 100MHz, so we must explicitly set the correct
 * values (48MHz is taken from rn_clk_mgr_construct()).
 */
static void dccg21_init(struct dccg *dccg)
{
	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

	if (dccg2_is_s0i3_golden_init_wa_done(dccg))
		return;

	/* 48MHz refclk from rn_clk_mgr_construct() */
	REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120230);
	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x0010bb80);
	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c);

	if (REG(REFCLK_CNTL))
		REG_WRITE(REFCLK_CNTL, 0);
}

static const struct dccg_funcs dccg21_funcs = {
	.update_dpp_dto = dccg21_update_dpp_dto,
	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
	.otg_add_pixel = dccg2_otg_add_pixel,
	.otg_drop_pixel = dccg2_otg_drop_pixel,
	.dccg_init = dccg21_init,
	.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
	.allow_clock_gating = dccg2_allow_clock_gating,
	.enable_memory_low_power = dccg2_enable_memory_low_power,
	.is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
};

struct dccg *dccg21_create(
	struct dc_context *ctx,
	const struct dccg_registers *regs,
	const struct dccg_shift *dccg_shift,
	const struct dccg_mask *dccg_mask)
{
	struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn);
	struct dccg *base;

	if (dccg_dcn == NULL) {
		BREAK_TO_DEBUGGER();
		return NULL;
	}

	base = &dccg_dcn->base;
	base->ctx = ctx;
	base->funcs = &dccg21_funcs;

	dccg_dcn->regs = regs;
	dccg_dcn->dccg_shift = dccg_shift;
	dccg_dcn->dccg_mask = dccg_mask;

	return &dccg_dcn->base;
}