Contributors: 6
| Author |
Tokens |
Token Proportion |
Commits |
Commit Proportion |
| Matthew Brost |
170 |
82.93% |
12 |
70.59% |
| Thomas Hellstrom |
19 |
9.27% |
1 |
5.88% |
| Stuart Summers |
6 |
2.93% |
1 |
5.88% |
| Brian Nguyen |
5 |
2.44% |
1 |
5.88% |
| Michal Wajdeczko |
4 |
1.95% |
1 |
5.88% |
| Sanjay Yadav |
1 |
0.49% |
1 |
5.88% |
| Total |
205 |
|
17 |
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2025 Intel Corporation
*/
#ifndef _XE_TLB_INVAL_H_
#define _XE_TLB_INVAL_H_
#include <linux/types.h>
#include "xe_tlb_inval_types.h"
struct xe_gt;
struct xe_guc;
struct xe_vm;
int xe_gt_tlb_inval_init_early(struct xe_gt *gt);
void xe_tlb_inval_reset(struct xe_tlb_inval *tlb_inval);
int xe_tlb_inval_all(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence);
int xe_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval);
void xe_tlb_inval_vm(struct xe_tlb_inval *tlb_inval, struct xe_vm *vm);
int xe_tlb_inval_range(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence,
u64 start, u64 end, u32 asid, struct drm_suballoc *prl_sa);
void xe_tlb_inval_fence_init(struct xe_tlb_inval *tlb_inval,
struct xe_tlb_inval_fence *fence,
bool stack);
/**
* xe_tlb_inval_fence_wait() - TLB invalidiation fence wait
* @fence: TLB invalidation fence to wait on
*
* Wait on a TLB invalidiation fence until it signals, non interruptible
*/
static inline void
xe_tlb_inval_fence_wait(struct xe_tlb_inval_fence *fence)
{
dma_fence_wait(&fence->base, false);
}
void xe_tlb_inval_done_handler(struct xe_tlb_inval *tlb_inval, int seqno);
bool xe_tlb_inval_idle(struct xe_tlb_inval *tlb_inval);
int xe_tlb_inval_range_tilemask_submit(struct xe_device *xe, u32 asid,
u64 start, u64 end, u8 tile_mask,
struct xe_tlb_inval_batch *batch);
void xe_tlb_inval_batch_wait(struct xe_tlb_inval_batch *batch);
#endif /* _XE_TLB_INVAL_ */