/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ #ifndef __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ #define __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ #define EN751221_XPON_PHY_RST 0 #define EN751221_PCM1_ZSI_ISI_RST 1 #define EN751221_FE_QDMA1_RST 2 #define EN751221_FE_QDMA2_RST 3 #define EN751221_FE_UNZIP_RST 4 #define EN751221_PCM2_RST 5 #define EN751221_PTM_MAC_RST 6 #define EN751221_CRYPTO_RST 7 #define EN751221_SAR_RST 8 #define EN751221_TIMER_RST 9 #define EN751221_INTC_RST 10 #define EN751221_BONDING_RST 11 #define EN751221_PCM1_RST 12 #define EN751221_UART_RST 13 #define EN751221_GPIO_RST 14 #define EN751221_GDMA_RST 15 #define EN751221_I2C_MASTER_RST 16 #define EN751221_PCM2_ZSI_ISI_RST 17 #define EN751221_SFC_RST 18 #define EN751221_UART2_RST 19 #define EN751221_GDMP_RST 20 #define EN751221_FE_RST 21 #define EN751221_USB_HOST_P0_RST 22 #define EN751221_GSW_RST 23 #define EN751221_SFC2_PCM_RST 24 #define EN751221_PCIE0_RST 25 #define EN751221_PCIE1_RST 26 #define EN751221_CPU_TIMER_RST 27 #define EN751221_PCIE_HB_RST 28 #define EN751221_SIMIF_RST 29 #define EN751221_XPON_MAC_RST 30 #define EN751221_GFAST_RST 31 #define EN751221_CPU_TIMER2_RST 32 #define EN751221_UART3_RST 33 #define EN751221_UART4_RST 34 #define EN751221_UART5_RST 35 #define EN751221_I2C2_RST 36 #define EN751221_XSI_MAC_RST 37 #define EN751221_XSI_PHY_RST 38 #define EN751221_DMT_RST 39 #define EN751221_USB_PHY_P0_RST 40 #define EN751221_USB_PHY_P1_RST 41 #endif /* __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ */