Contributors: 8
Author Tokens Token Proportion Commits Commit Proportion
Mukul Joshi 253 71.07% 4 25.00%
Ben Goz 51 14.33% 3 18.75%
Harish Kasiviswanathan 20 5.62% 1 6.25%
Jack Xiao 16 4.49% 1 6.25%
Oded Gabbay 10 2.81% 3 18.75%
Yong Zhao 3 0.84% 2 12.50%
Lang Yu 2 0.56% 1 6.25%
Rajneesh Bhardwaj 1 0.28% 1 6.25%
Total 356 16 


// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2025 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "kfd_device_queue_manager.h"
#include "gc/gc_12_1_0_sh_mask.h"
#include "soc_v1_0_enum.h"

static int update_qpd_v12_1(struct device_queue_manager *dqm,
			 struct qcm_process_device *qpd);
static void init_sdma_vm_v12_1(struct device_queue_manager *dqm, struct queue *q,
			    struct qcm_process_device *qpd);

void device_queue_manager_init_v12_1(
	struct device_queue_manager_asic_ops *asic_ops)
{
	asic_ops->update_qpd = update_qpd_v12_1;
	asic_ops->init_sdma_vm = init_sdma_vm_v12_1;
	asic_ops->mqd_manager_init = mqd_manager_init_v12_1;
}

static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
{
	uint32_t shared_base = pdd->lds_base >> 48;
	uint32_t private_base = pdd->scratch_base >> 58;

	return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
		(private_base << SH_MEM_BASES__PRIVATE_BASE__SHIFT);
}

static int update_qpd_v12_1(struct device_queue_manager *dqm,
			 struct qcm_process_device *qpd)
{
	struct kfd_process_device *pdd;
	struct amdgpu_device *adev = dqm->dev->adev;
	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
	bool xnack_enabled;

	pdd = qpd_to_pdd(qpd);
	qpd->vm_cntx_cntl = hub->vm_cntx_cntl;

	/* check if sh_mem_config register already configured */
	if (qpd->sh_mem_config == 0) {
		qpd->sh_mem_config =
			(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
				SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
			(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);

		qpd->sh_mem_config |=
			(1 << SH_MEM_CONFIG__F8_MODE__SHIFT);
		qpd->sh_mem_ape1_limit = 0;
		qpd->sh_mem_ape1_base = 0;
	}

	xnack_enabled = KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev) ?
			pdd->process->xnack_enabled :
			!pdd->dev->kfd->noretry;

	if (!xnack_enabled) {
		qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
		qpd->vm_cntx_cntl &=
			~(1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT);
	} else {
		qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT);
		qpd->vm_cntx_cntl |=
			(1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT);
	}

	qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);

	pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);

	return 0;
}

static void init_sdma_vm_v12_1(struct device_queue_manager *dqm, struct queue *q,
			    struct qcm_process_device *qpd)
{
	/* Not needed on SDMAv4 onwards any more */
	q->properties.sdma_vm_addr = 0;
}