Contributors: 14
Author Tokens Token Proportion Commits Commit Proportion
Bhawanpreet Lakha 240 50.42% 1 5.56%
Harry Wentland 110 23.11% 4 22.22%
Bhuvana Chandra Pinninti 22 4.62% 1 5.56%
Roman Li 21 4.41% 1 5.56%
Nicholas Kazlauskas 21 4.41% 1 5.56%
Aurabindo Pillai 17 3.57% 1 5.56%
Wesley Chalmers 15 3.15% 2 11.11%
Hansen 9 1.89% 1 5.56%
Qingqing Zhuo 8 1.68% 1 5.56%
George Shen 4 0.84% 1 5.56%
Daniel Miess 3 0.63% 1 5.56%
Kees Cook 2 0.42% 1 5.56%
Eric Yang 2 0.42% 1 5.56%
Dmytro Laktyushkin 2 0.42% 1 5.56%
Total 476 18 


/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "reg_helper.h"
#include "core_types.h"
#include "dcn30_dccg.h"

#define TO_DCN_DCCG(dccg)\
	container_of(dccg, struct dcn_dccg, base)

#define REG(reg) \
	(dccg_dcn->regs->reg)

#undef FN
#define FN(reg_name, field_name) \
	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

#define CTX \
	dccg_dcn->base.ctx
#define DC_LOGGER \
	dccg->ctx->logger

void dccg3_enable_hdmicharclk(struct dccg *dccg, int hpo_inst, int phypll_inst)
{
	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

	ASSERT(hpo_inst >= 0 && phypll_inst >= 0);
	REG_UPDATE_2(HDMICHARCLK_CLOCK_CNTL[hpo_inst],
			HDMICHARCLK0_EN, 1,
			HDMICHARCLK0_SRC_SEL, phypll_inst);

	/* Enable FORCE_EN for SYMCLK */
	switch (phypll_inst) {
	case 0:
		REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
				PHYASYMCLK_FORCE_EN, 1,
				PHYASYMCLK_FORCE_SRC_SEL, 1);
		break;
	case 1:
		REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
				PHYBSYMCLK_FORCE_EN, 1,
				PHYBSYMCLK_FORCE_SRC_SEL, 1);
		break;
	case 2:
		REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
				PHYCSYMCLK_FORCE_EN, 1,
				PHYCSYMCLK_FORCE_SRC_SEL, 1);
		break;
	default:
		BREAK_TO_DEBUGGER();
		return;
	}
}

void dccg3_disable_hdmicharclk(struct dccg *dccg, int hpo_inst)
{
	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

	REG_WRITE(HDMICHARCLK_CLOCK_CNTL[hpo_inst], 0);
}

static const struct dccg_funcs dccg3_funcs = {
	.enable_hdmicharclk = dccg3_enable_hdmicharclk,
	.disable_hdmicharclk = dccg3_disable_hdmicharclk,
	.update_dpp_dto = dccg2_update_dpp_dto,
	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
	.otg_add_pixel = dccg2_otg_add_pixel,
	.otg_drop_pixel = dccg2_otg_drop_pixel,
	.dccg_init = dccg2_init,
	.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
	.allow_clock_gating = dccg2_allow_clock_gating,
	.enable_memory_low_power = dccg2_enable_memory_low_power,
	.is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
};

struct dccg *dccg3_create(
	struct dc_context *ctx,
	const struct dccg_registers *regs,
	const struct dccg_shift *dccg_shift,
	const struct dccg_mask *dccg_mask)
{
	struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn);
	struct dccg *base;

	if (dccg_dcn == NULL) {
		BREAK_TO_DEBUGGER();
		return NULL;
	}

	base = &dccg_dcn->base;
	base->ctx = ctx;
	base->funcs = &dccg3_funcs;

	dccg_dcn->regs = regs;
	dccg_dcn->dccg_shift = dccg_shift;
	dccg_dcn->dccg_mask = dccg_mask;

	return &dccg_dcn->base;
}

struct dccg *dccg30_create(
	struct dc_context *ctx,
	const struct dccg_registers *regs,
	const struct dccg_shift *dccg_shift,
	const struct dccg_mask *dccg_mask)
{
	struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn);
	struct dccg *base;

	if (dccg_dcn == NULL) {
		BREAK_TO_DEBUGGER();
		return NULL;
	}

	base = &dccg_dcn->base;
	base->ctx = ctx;
	base->funcs = &dccg3_funcs;

	dccg_dcn->regs = regs;
	dccg_dcn->dccg_shift = dccg_shift;
	dccg_dcn->dccg_mask = dccg_mask;

	return &dccg_dcn->base;
}