| Author | Tokens | Token Proportion | Commits | Commit Proportion |
|---|---|---|---|---|
| Kaustabh Chakraborty | 788 | 99.62% | 1 | 33.33% |
| Sangbeom Kim | 2 | 0.25% | 1 | 33.33% |
| Krzysztof Kozlowski | 1 | 0.13% | 1 | 33.33% |
| Total | 791 | 3 |
/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (c) 2015 Samsung Electronics Co., Ltd * Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org> * Copyright (c) 2026 Łukasz Lebiedziński <kernel@lvkasz.us> */ #ifndef __LINUX_MFD_S2MU005_H #define __LINUX_MFD_S2MU005_H #include <linux/bitfield.h> #include <linux/bits.h> /* S2MU005 registers */ enum s2mu005_reg { S2MU005_REG_CHGR_INT1, S2MU005_REG_CHGR_INT1M, S2MU005_REG_FLED_INT1, S2MU005_REG_FLED_INT1M, S2MU005_REG_MUIC_INT1, S2MU005_REG_MUIC_INT2, S2MU005_REG_MUIC_INT1M, S2MU005_REG_MUIC_INT2M, S2MU005_REG_CHGR_STATUS0, S2MU005_REG_CHGR_STATUS1, S2MU005_REG_CHGR_STATUS2, S2MU005_REG_CHGR_STATUS3, S2MU005_REG_CHGR_STATUS4, S2MU005_REG_CHGR_STATUS5, S2MU005_REG_CHGR_CTRL0, S2MU005_REG_CHGR_CTRL1, S2MU005_REG_CHGR_CTRL2, S2MU005_REG_CHGR_CTRL3, S2MU005_REG_CHGR_CTRL4, S2MU005_REG_CHGR_CTRL5, S2MU005_REG_CHGR_CTRL6, S2MU005_REG_CHGR_CTRL7, S2MU005_REG_CHGR_CTRL8, S2MU005_REG_CHGR_CTRL9, S2MU005_REG_CHGR_CTRL10, S2MU005_REG_CHGR_CTRL11, S2MU005_REG_CHGR_CTRL12, S2MU005_REG_CHGR_CTRL13, S2MU005_REG_CHGR_CTRL14, S2MU005_REG_CHGR_CTRL15, S2MU005_REG_CHGR_CTRL16, S2MU005_REG_CHGR_CTRL17, S2MU005_REG_CHGR_CTRL18, S2MU005_REG_CHGR_CTRL19, S2MU005_REG_CHGR_TEST0, S2MU005_REG_CHGR_TEST1, S2MU005_REG_CHGR_TEST2, S2MU005_REG_CHGR_TEST3, S2MU005_REG_CHGR_TEST4, S2MU005_REG_CHGR_TEST5, S2MU005_REG_CHGR_TEST6, S2MU005_REG_CHGR_TEST7, S2MU005_REG_CHGR_TEST8, S2MU005_REG_CHGR_TEST9, S2MU005_REG_CHGR_TEST10, S2MU005_REG_FLED_STATUS, S2MU005_REG_FLED_CH0_CTRL0, S2MU005_REG_FLED_CH0_CTRL1, S2MU005_REG_FLED_CH0_CTRL2, S2MU005_REG_FLED_CH0_CTRL3, S2MU005_REG_FLED_CH1_CTRL0, S2MU005_REG_FLED_CH1_CTRL1, S2MU005_REG_FLED_CH1_CTRL2, S2MU005_REG_FLED_CH1_CTRL3, S2MU005_REG_FLED_CTRL0, S2MU005_REG_FLED_CTRL1, S2MU005_REG_FLED_CTRL2, S2MU005_REG_FLED_CTRL3, S2MU005_REG_FLED_CTRL4, S2MU005_REG_FLED_CTRL5, S2MU005_REG_FLED_CTRL6, S2MU005_REG_RGB_EN, S2MU005_REG_RGB_CH0_CTRL, S2MU005_REG_RGB_CH1_CTRL, S2MU005_REG_RGB_CH2_CTRL, S2MU005_REG_RGB_CH0_RAMP, S2MU005_REG_RGB_CH0_STAY, S2MU005_REG_RGB_CH1_RAMP, S2MU005_REG_RGB_CH1_STAY, S2MU005_REG_RGB_CH2_RAMP, S2MU005_REG_RGB_CH2_STAY, S2MU005_REG_RGB_TEST0, S2MU005_REG_RGB_CTRL0, S2MU005_REG_MUIC_ADC, S2MU005_REG_MUIC_DEV1, S2MU005_REG_MUIC_DEV2, S2MU005_REG_MUIC_DEV3, S2MU005_REG_MUIC_BUTTON1, S2MU005_REG_MUIC_BUTTON2, S2MU005_REG_MUIC_RESET, S2MU005_REG_MUIC_CHGTYPE, S2MU005_REG_MUIC_DEVAPPLE, S2MU005_REG_MUIC_BCDRESCAN, S2MU005_REG_MUIC_TEST1, S2MU005_REG_MUIC_TEST2, S2MU005_REG_MUIC_TEST3, S2MU005_REG_ID = 0x73, S2MU005_REG_MUIC_CTRL1 = 0xb2, S2MU005_REG_MUIC_TIMERSET1, S2MU005_REG_MUIC_TIMERSET2, S2MU005_REG_MUIC_SWCTRL, S2MU005_REG_MUIC_TIMERSET3, S2MU005_REG_MUIC_CTRL2, S2MU005_REG_MUIC_CTRL3, S2MU005_REG_MUIC_LDOADC_L = 0xbf, S2MU005_REG_MUIC_LDOADC_H, }; #define S2MU005_REG_FLED_CH_CTRL0(x) (S2MU005_REG_FLED_CH0_CTRL0 + 4 * (x)) #define S2MU005_REG_FLED_CH_CTRL1(x) (S2MU005_REG_FLED_CH0_CTRL1 + 4 * (x)) #define S2MU005_REG_FLED_CH_CTRL2(x) (S2MU005_REG_FLED_CH0_CTRL2 + 4 * (x)) #define S2MU005_REG_FLED_CH_CTRL3(x) (S2MU005_REG_FLED_CH0_CTRL3 + 4 * (x)) #define S2MU005_REG_RGB_CH_CTRL(x) (S2MU005_REG_RGB_CH0_CTRL + 1 * (x)) #define S2MU005_REG_RGB_CH_RAMP(x) (S2MU005_REG_RGB_CH0_RAMP + 2 * (x)) #define S2MU005_REG_RGB_CH_STAY(x) (S2MU005_REG_RGB_CH0_STAY + 2 * (x)) /* S2MU005_REG_CHGR_STATUS0 */ #define S2MU005_CHGR_VBUS BIT(7) #define S2MU005_CHGR_WCIN BIT(6) #define S2MU005_CHGR_VMID BIT(5) #define S2MU005_CHGR_CHG BIT(4) #define S2MU005_CHGR_STAT GENMASK(3, 0) #define S2MU005_CHGR_STAT_DONE 8 #define S2MU005_CHGR_STAT_TOPOFF 7 #define S2MU005_CHGR_STAT_DONE_FLAG 6 #define S2MU005_CHGR_STAT_CV 5 #define S2MU005_CHGR_STAT_CC 4 #define S2MU005_CHGR_STAT_COOL_CHG 3 #define S2MU005_CHGR_STAT_PRE_CHG 2 /* S2MU005_REG_CHGR_STATUS1 */ #define S2MU005_CHGR_DETBAT BIT(7) #define S2MU005_CHGR_VBUS_OVP GENMASK(6, 4) #define S2MU005_CHGR_VBUS_OVP_OVERVOLT 2 /* S2MU005_REG_CHGR_STATUS2 */ #define S2MU005_CHGR_BAT GENMASK(6, 4) #define S2MU005_CHGR_BAT_VOLT_DET 7 #define S2MU005_CHGR_BAT_FAST_CHG_DET 6 #define S2MU005_CHGR_BAT_COOL_CHG_DET 5 #define S2MU005_CHGR_BAT_LOW_CHG 2 #define S2MU005_CHGR_BAT_SELF_DISCHG 1 #define S2MU005_CHGR_BAT_OVP_DET 0 /* S2MU005_REG_CHGR_STATUS3 */ #define S2MU005_CHGR_EVT GENMASK(3, 0) #define S2MU005_CHGR_EVT_WDT_RST 6 #define S2MU005_CHGR_EVT_WDT_SUSP 5 #define S2MU005_CHGR_EVT_VSYS_VUVLO 4 #define S2MU005_CHGR_EVT_VSYS_VOVP 3 #define S2MU005_CHGR_EVT_THERM_FOLDBACK 2 #define S2MU005_CHGR_EVT_THERM_SHUTDOWN 1 /* S2MU005_REG_CHGR_CTRL0 */ #define S2MU005_CHGR_CHG_EN BIT(4) #define S2MU005_CHGR_OP_MODE GENMASK(2, 0) #define S2MU005_CHGR_OP_MODE_OTG BIT(2) #define S2MU005_CHGR_OP_MODE_CHG BIT(1) /* S2MU005_REG_CHGR_CTRL1 */ #define S2MU005_CHGR_VIN_DROP GENMASK(6, 4) /* S2MU005_REG_CHGR_CTRL2 */ #define S2MU005_CHGR_IN_CURR_LIM GENMASK(5, 0) /* S2MU005_REG_CHGR_CTRL4 */ #define S2MU005_CHGR_OTG_OCP_ON BIT(5) #define S2MU005_CHGR_OTG_OCP_OFF BIT(4) #define S2MU005_CHGR_OTG_OCP GENMASK(3, 2) #define S2MU005_CHGR_OTG_OCP_1P5A 0x3 /* S2MU005_REG_CHGR_CTRL5 */ #define S2MU005_CHGR_VMID_BOOST GENMASK(4, 0) #define S2MU005_CHGR_VMID_BOOST_5P1V 0x16 /* S2MU005_REG_CHGR_CTRL6 */ #define S2MU005_CHGR_COOL_CHG_CURR GENMASK(5, 0) /* S2MU005_REG_CHGR_CTRL7 */ #define S2MU005_CHGR_FAST_CHG_CURR GENMASK(5, 0) /* S2MU005_REG_CHGR_CTRL8 */ #define S2MU005_CHGR_VF_VBAT GENMASK(6, 1) /* S2MU005_REG_CHGR_CTRL10 */ #define S2MU005_CHGR_TOPOFF_CURR(x) (GENMASK(3, 0) << 4 * (x)) /* S2MU005_REG_CHGR_CTRL11 */ #define S2MU005_CHGR_OSC_BOOST GENMASK(6, 5) #define S2MU005_CHGR_OSC_BUCK GENMASK(4, 3) #define S2MU005_CHGR_OSC_BOOST_2MHZ 0x3 /* S2MU005_REG_CHGR_CTRL12 */ #define S2MU005_CHGR_WDT GENMASK(2, 0) #define S2MU005_CHGR_WDT_ON BIT(2) #define S2MU005_CHGR_WDT_OFF BIT(1) /* S2MU005_REG_CHGR_CTRL15 */ #define S2MU005_CHGR_OTG_EN GENMASK(3, 2) #define S2MU005_CHGR_OTG_EN_ON 0x3 /* S2MU005_REG_FLED_STATUS */ #define S2MU005_FLED_FLASH_STATUS(x) (BIT(7) >> 2 * (x)) #define S2MU005_FLED_TORCH_STATUS(x) (BIT(6) >> 2 * (x)) /* S2MU005_REG_FLED_CHx_CTRL0 */ #define S2MU005_FLED_FLASH_IOUT GENMASK(3, 0) /* S2MU005_REG_FLED_CHx_CTRL1 */ #define S2MU005_FLED_TORCH_IOUT GENMASK(3, 0) /* S2MU005_REG_FLED_CHx_CTRL2 */ #define S2MU005_FLED_TORCH_TIMEOUT GENMASK(3, 0) /* S2MU005_REG_FLED_CHx_CTRL3 */ #define S2MU005_FLED_FLASH_TIMEOUT GENMASK(3, 0) /* S2MU005_REG_FLED_CTRL1 */ #define S2MU005_FLED_CH_EN BIT(7) /* * S2MU005_REG_FLED_CTRL4 - Rev. EVT0 * S2MU005_REG_FLED_CTRL6 - Rev. EVT1 and later */ #define S2MU005_FLED_FLASH_EN(x) (GENMASK(7, 6) >> 4 * (x)) #define S2MU005_FLED_TORCH_EN(x) (GENMASK(5, 4) >> 4 * (x)) /* S2MU005_REG_RGB_EN */ #define S2MU005_RGB_RESET BIT(6) #define S2MU005_RGB_SLOPE GENMASK(5, 0) #define S2MU005_RGB_SLOPE_CONST (BIT(4) | BIT(2) | BIT(0)) #define S2MU005_RGB_SLOPE_SMOOTH (BIT(5) | BIT(3) | BIT(1)) /* S2MU005_REG_RGB_CHx_RAMP */ #define S2MU005_RGB_CH_RAMP_UP GENMASK(7, 4) #define S2MU005_RGB_CH_RAMP_DN GENMASK(3, 0) /* S2MU005_REG_RGB_CHx_STAY */ #define S2MU005_RGB_CH_STAY_HI GENMASK(7, 4) #define S2MU005_RGB_CH_STAY_LO GENMASK(3, 0) /* S2MU005_REG_MUIC_DEV1 */ #define S2MU005_MUIC_OTG BIT(7) #define S2MU005_MUIC_DCP BIT(6) #define S2MU005_MUIC_CDP BIT(5) #define S2MU005_MUIC_T1_T2_CHG BIT(4) #define S2MU005_MUIC_UART BIT(3) #define S2MU005_MUIC_SDP BIT(2) #define S2MU005_MUIC_LANHUB BIT(1) #define S2MU005_MUIC_AUDIO BIT(0) /* S2MU005_REG_MUIC_DEV2 */ #define S2MU005_MUIC_SDP_1P8S BIT(7) #define S2MU005_MUIC_AV BIT(6) #define S2MU005_MUIC_TTY BIT(5) #define S2MU005_MUIC_PPD BIT(4) #define S2MU005_MUIC_JIG_UART_OFF BIT(3) #define S2MU005_MUIC_JIG_UART_ON BIT(2) #define S2MU005_MUIC_JIG_USB_OFF BIT(1) #define S2MU005_MUIC_JIG_USB_ON BIT(0) /* S2MU005_REG_MUIC_DEV3 */ #define S2MU005_MUIC_U200_CHG BIT(7) #define S2MU005_MUIC_VBUS_AV BIT(4) #define S2MU005_MUIC_VBUS_R255 BIT(1) #define S2MU005_MUIC_MHL BIT(0) /* S2MU005_REG_MUIC_DEVAPPLE */ #define S2MU005_MUIC_APPLE_CHG_0P5A BIT(7) #define S2MU005_MUIC_APPLE_CHG_1P0A BIT(6) #define S2MU005_MUIC_APPLE_CHG_2P0A BIT(5) #define S2MU005_MUIC_APPLE_CHG_2P4A BIT(4) #define S2MU005_MUIC_SDP_DCD_OUT BIT(3) #define S2MU005_MUIC_RID_WAKEUP BIT(2) #define S2MU005_MUIC_VBUS_WAKEUP BIT(1) #define S2MU005_MUIC_BCV1P2_OR_OPEN BIT(0) /* S2MU005_REG_ID */ #define S2MU005_ID_MASK GENMASK(3, 0) /* S2MU005_REG_MUIC_SWCTRL */ #define S2MU005_MUIC_DM_DP GENMASK(7, 2) #define S2MU005_MUIC_JIG BIT(0) #define S2MU005_MUIC_DM_DP_UART 0x12 #define S2MU005_MUIC_DM_DP_USB 0x09 /* S2MU005_REG_MUIC_CTRL1 */ #define S2MU005_MUIC_OPEN BIT(4) #define S2MU005_MUIC_RAW_DATA BIT(3) #define S2MU005_MUIC_MAN_SW BIT(2) #define S2MU005_MUIC_WAIT BIT(1) #define S2MU005_MUIC_IRQ BIT(0) /* S2MU005_REG_MUIC_CTRL3 */ #define S2MU005_MUIC_ONESHOT_ADC BIT(2) /* S2MU005_REG_MUIC_LDOADC_L and S2MU005_REG_MUIC_LDOADC_H */ #define S2MU005_MUIC_VSET GENMASK(4, 0) #define S2MU005_MUIC_VSET_3P0V 0x1f #define S2MU005_MUIC_VSET_2P6V 0x0e #define S2MU005_MUIC_VSET_2P4V 0x0c #define S2MU005_MUIC_VSET_2P2V 0x0a #define S2MU005_MUIC_VSET_2P0V 0x08 #define S2MU005_MUIC_VSET_1P5V 0x03 #define S2MU005_MUIC_VSET_1P4V 0x02 #define S2MU005_MUIC_VSET_1P2V 0x00 #endif /* __LINUX_MFD_S2MU005_H */
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