Files:

    Name Lines Files Authors Tokens   Color Graph By Token Proportion
    arc_farm_arc0_acp_eng_regs.h 567 - 1 1100
    arc_farm_arc0_aux_masks.h 819 - 1 1999
    arc_farm_arc0_aux_regs.h 591 - 1 1148
    arc_farm_arc0_dup_eng_axuser_regs.h 61 - 1 88
    arc_farm_arc0_dup_eng_regs.h 575 - 1 1116
    arc_farm_kdma_ctx_axuser_masks.h 135 - 1 327
    arc_farm_kdma_ctx_axuser_regs.h 61 - 1 88
    arc_farm_kdma_ctx_masks.h 221 - 1 552
    arc_farm_kdma_ctx_regs.h 95 - 1 156
    arc_farm_kdma_kdma_cgm_regs.h 29 - 1 24
    arc_farm_kdma_masks.h 415 - 1 1111
    arc_farm_kdma_regs.h 157 - 1 280
    cpu_if_regs.h 777 - 1 1520
    dcore0_dec0_cmd_masks.h 229 - 1 619
    dcore0_dec0_cmd_regs.h 85 - 1 136
    dcore0_edma0_core_ctx_axuser_regs.h 61 - 1 88
    dcore0_edma0_core_ctx_regs.h 95 - 1 156
    dcore0_edma0_core_masks.h 415 - 1 1111
    dcore0_edma0_core_regs.h 157 - 1 280
    dcore0_edma0_qm_arc_aux_regs.h 591 - 1 1148
    dcore0_edma0_qm_axuser_nonsecured_regs.h 61 - 1 88
    dcore0_edma0_qm_cgm_regs.h 29 - 1 24
    dcore0_edma0_qm_masks.h 1165 - 1 3264
    dcore0_edma0_qm_regs.h 1057 - 1 2080
    dcore0_edma1_core_ctx_axuser_regs.h 61 - 1 88
    dcore0_edma1_qm_axuser_nonsecured_regs.h 61 - 1 88
    dcore0_hmmu0_mmu_masks.h 289 - 1 719
    dcore0_hmmu0_mmu_regs.h 237 - 1 440
    dcore0_hmmu0_stlb_masks.h 333 - 1 839
    dcore0_hmmu0_stlb_regs.h 141 - 1 248
    dcore0_mme_acc_regs.h 73 - 1 112
    dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h 33 - 1 32
    dcore0_mme_ctrl_lo_arch_base_addr_regs.h 39 - 1 44
    dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h 71 - 1 108
    dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h 35 - 1 36
    dcore0_mme_ctrl_lo_arch_tensor_a_regs.h 67 - 1 100
    dcore0_mme_ctrl_lo_arch_tensor_b_regs.h 67 - 1 100
    dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h 67 - 1 100
    dcore0_mme_ctrl_lo_masks.h 465 - 1 1290
    dcore0_mme_ctrl_lo_mme_axuser_regs.h 61 - 1 88
    dcore0_mme_ctrl_lo_regs.h 163 - 1 292
    dcore0_mme_qm_arc_acp_eng_regs.h 567 - 1 1100
    dcore0_mme_qm_arc_aux_regs.h 591 - 1 1148
    dcore0_mme_qm_arc_dup_eng_axuser_regs.h 61 - 1 88
    dcore0_mme_qm_arc_dup_eng_regs.h 575 - 1 1116
    dcore0_mme_qm_axuser_nonsecured_regs.h 61 - 1 88
    dcore0_mme_qm_axuser_secured_regs.h 61 - 1 88
    dcore0_mme_qm_cgm_regs.h 29 - 1 24
    dcore0_mme_qm_regs.h 1057 - 1 2080
    dcore0_mme_sbte0_masks.h 107 - 1 222
    dcore0_mme_sbte0_mstr_if_axuser_regs.h 61 - 1 88
    dcore0_mme_wb0_mstr_if_axuser_regs.h 61 - 1 88
    dcore0_rtr0_ctrl_regs.h 291 - 1 548
    dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h 213 - 1 392
    dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h 189 - 1 344
    dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h 213 - 1 392
    dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h 189 - 1 344
    dcore0_sync_mngr_glbl_masks.h 135 - 1 299
    dcore0_sync_mngr_glbl_regs.h 1203 - 1 2372
    dcore0_sync_mngr_mstr_if_axuser_masks.h 135 - 1 327
    dcore0_sync_mngr_mstr_if_axuser_regs.h 61 - 1 88
    dcore0_sync_mngr_objs_masks.h 87 - 1 205
    dcore0_sync_mngr_objs_regs.h 43543 - 1 87052
    dcore0_tpc0_cfg_axuser_regs.h 61 - 1 88
    dcore0_tpc0_cfg_kernel_regs.h 129 - 1 224
    dcore0_tpc0_cfg_kernel_tensor_0_regs.h 63 - 1 92
    dcore0_tpc0_cfg_masks.h 509 - 1 1410
    dcore0_tpc0_cfg_qm_regs.h 129 - 1 224
    dcore0_tpc0_cfg_qm_sync_object_regs.h 27 - 1 20
    dcore0_tpc0_cfg_qm_tensor_0_regs.h 63 - 1 92
    dcore0_tpc0_cfg_regs.h 229 - 1 424
    dcore0_tpc0_cfg_special_regs.h 185 - 1 336
    dcore0_tpc0_eml_busmon_0_regs.h 163 - 1 292
    dcore0_tpc0_eml_etf_regs.h 113 - 1 192
    dcore0_tpc0_eml_funnel_regs.h 75 - 1 116
    dcore0_tpc0_eml_spmu_regs.h 151 - 1 268
    dcore0_tpc0_eml_stm_regs.h 131 - 1 228
    dcore0_tpc0_qm_arc_aux_regs.h 591 - 1 1148
    dcore0_tpc0_qm_axuser_nonsecured_regs.h 61 - 1 88
    dcore0_tpc0_qm_cgm_regs.h 29 - 1 24
    dcore0_tpc0_qm_regs.h 1057 - 1 2080
    dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h 61 - 1 88
    dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h 61 - 1 88
    dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h 61 - 1 88
    dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h 61 - 1 88
    dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h 61 - 1 88
    dcore0_vdec0_brdg_ctrl_masks.h 579 - 1 1459
    dcore0_vdec0_brdg_ctrl_regs.h 245 - 1 456
    dcore0_vdec0_ctrl_special_regs.h 185 - 1 336
    dcore1_mme_ctrl_lo_regs.h 163 - 1 292
    dcore1_sync_mngr_glbl_regs.h 1203 - 2 2372
    dcore3_mme_ctrl_lo_regs.h 163 - 1 292
    gaudi2_blocks_linux_driver.h 45067 - 1 180211
    gaudi2_regs.h 572 - 6 1330
    nic0_qm0_cgm_regs.h 29 - 1 24
    nic0_qm0_regs.h 1057 - 1 2080
    nic0_qm_arc_aux0_regs.h 591 - 1 1148
    nic0_qpc0_regs.h 905 - 1 1776
    nic0_umr0_0_completion_queue_ci_1_regs.h 27 - 1 20
    nic0_umr0_0_unsecure_doorbell0_regs.h 31 - 1 28
    pcie_aux_regs.h 293 - 1 552
    pcie_dbi_regs.h 421 - 1 808
    pcie_dec0_cmd_masks.h 229 - 1 619
    pcie_dec0_cmd_regs.h 85 - 1 136
    pcie_vdec0_brdg_ctrl_axuser_dec_regs.h 61 - 1 88
    pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h 61 - 1 88
    pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h 61 - 1 88
    pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h 61 - 1 88
    pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h 61 - 1 88
    pcie_vdec0_brdg_ctrl_masks.h 579 - 1 1459
    pcie_vdec0_brdg_ctrl_regs.h 245 - 1 456
    pcie_vdec0_ctrl_special_regs.h 185 - 1 336
    pcie_wrap_regs.h 601 - 1 1168
    pcie_wrap_special_regs.h 185 - 2 336
    pdma0_core_ctx_axuser_regs.h 61 - 1 88
    pdma0_core_ctx_regs.h 95 - 1 156
    pdma0_core_masks.h 415 - 1 1111
    pdma0_core_regs.h 157 - 1 280
    pdma0_core_special_masks.h 135 - 1 348
    pdma0_qm_arc_aux_regs.h 591 - 1 1148
    pdma0_qm_axuser_nonsecured_regs.h 61 - 1 88
    pdma0_qm_axuser_secured_regs.h 61 - 1 88
    pdma0_qm_cgm_regs.h 29 - 1 24
    pdma0_qm_masks.h 1165 - 1 3264
    pdma0_qm_regs.h 1057 - 1 2080
    pdma1_core_ctx_axuser_regs.h 61 - 1 88
    pdma1_qm_axuser_nonsecured_regs.h 61 - 1 88
    pmmu_hbw_stlb_masks.h 333 - 1 839
    pmmu_hbw_stlb_regs.h 141 - 1 248
    pmmu_pif_regs.h 135 - 1 236
    psoc_etr_masks.h 311 - 1 842
    psoc_etr_regs.h 115 - 1 196
    psoc_global_conf_masks.h 1397 - 1 3975
    psoc_global_conf_regs.h 1337 - 1 2640
    psoc_reset_conf_masks.h 2321 - 1 5823
    psoc_reset_conf_regs.h 989 - 1 1944
    psoc_timestamp_regs.h 57 - 1 80
    rot0_desc_regs.h 155 - 1 276
    rot0_masks.h 313 - 1 864
    rot0_qm_arc_aux_regs.h 591 - 1 1148
    rot0_qm_axuser_nonsecured_regs.h 61 - 1 88
    rot0_qm_cgm_regs.h 29 - 1 24
    rot0_qm_regs.h 1057 - 1 2080
    rot0_regs.h 111 - 1 188
    xbar_edge_0_regs.h 199 - 1 364
    xbar_mid_0_regs.h 199 - 1 364